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CS5150
CS5150
CPU 4-Bit Synchronous Buck Controller
Description
The CS5150 is a 4-bit synchronous dual N-Channel buck controller. It is designed to provide unprecedented transient response for today's demanding high-density, high-speed logic. The regulator operates using a proprietary control method, which allows a 100ns response time to load transients. The CS5150 is designed to operate over a 4.25-16V range (VCC) using 12V to power the IC and 5V as the main supply for conversion. The CS5150 is specifically designed to power Pentium(R) Pro processors and other high performance core logic. It includes the following features: on board, 4-bit DAC, short circuit protection, 1.0% output tolerance, VCC monitor, and programmable soft start capability. The CS5150 is upward compatible with the 5-bit CS5155, allowing the mother board designer the capability of using either the CS5150 or the CS5155 with no change in layout. The CS5150 is available in 16 pin surface mount and DIP packages.
Features
s Dual N-Channel Design s Excess of 1MHz Operation s 100ns Transient Response s 4-Bit DAC s Upward Compatible with 5-Bit CS5155/5156 and Adjustable CS5120/5121 s 30ns Gate Rise/Fall Times s 1% DAC Accuracy s 5V & 12V Operation s Remote Sense s Programmable Soft Start s Lossless Short Circuit Protection
Application Diagram Switching Power Supply for core logic - Pentium(R) Pro processor
12V 5V
s VCC Monitor s 25ns FET Nonoverlap Time s Adaptive Voltage Positioning s V2TM Control Topology s Current Sharing s Overvoltage Protection
2H 2.1V to 3.5V @ 13A
0.1F
1200F/16V x 3 AlEl IRL3103
VCC1 VCC2 VID0 VID1 VID2 VID3 VID0 VID1 VID2 VID3 COFF 330pF SS 0.1F 0.33F COMP LGnd
VGATE(H)
Package Options
CS5150
VGATE(L) IRL3103 1200F/16V x 5 AlEl PGnd VFB VFFB 3.3k
16 Lead SO Narrow & PDIP
VID0 VID1 VID2 VID3 SS NC COFF VFFB
1
VFB COMP LGnd VCC1 VGATE(L) PGnd VGATE(H) VCC2
100pF
V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation. Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com
Rev. 1/4/99
1
A
(R)
Company
CS5150
Absolute Maximum Ratings Pin Name Max Operating Voltage Max Current VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA DC/1.5A peak VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA DC/1.5A peak SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-100A COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200A VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A COFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A VFFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.2A VID0 - VID3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-50A VGATE(H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak VGATE(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16V/-0.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak LGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA PGnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA DC/1.5A peak Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 150C Lead Temperature Soldering Wave Solder (through hole styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sec. max, 260C peak Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183C, 230C peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to 150C ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Electrical Characteristics: 0C < TA < +70C; 0C < TJ < +85C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID2 = VID1 =
VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1F, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT
s Error Amplifier VFB Bias Current Open Loop Gain Unity Gain Bandwidth COMP SINK Current COMP SOURCE Current COMP CLAMP Current COMP High Voltage COMP Low Voltage PSRR s VCC1 Monitor Start Threshold Stop Threshold Hysteresis s DAC Input Threshold Input Pull Up Resistance Pull Up Voltage Accuracy VID3 VID2 VID1 VID0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0
VFB = 0V 1.25V < VCOMP < 4V; Note 1 Note 1 VCOMP = 1.5V; VFB = 3V; VSS > 2V VCOMP = 1.2V; VFB = 2.7V; VSS = 5V VCOMP = 0V; VFB = 2.7V VFB = 2.7V; VSS = 5V VFB =3V 8V < VCC1 < 14V @ 1kHz; Note 1
50 500 0.4 30 0.4 4.0 60
0.3 60 3000 2.5 50 1.0 4.3 160 85
1.0
8.0 70 1.6 5.0 600
A dB kH mA A mA V mV dB
Output switching Output not switching Start-Stop
3.75 3.70
3.90 3.85 50
4.05 4.00
V V mV
VID0, VID1, VID2, VID3 VID0, VID1, VID2, VID3 Measure VFB = VCOMP, 25C TJ 85C
1.00 25 4.85
1.25 50 5.00
2.40 100 5.15 1.0 1.2564 2.1614 2.2624 2.3634 2.4644 2.5654 2.6664 2.7674 2.8684 2.9694
V k V % V V V V V V V V V V
1.2315 2.1186 2.2176 2.3166 2.4156 2.5146 2.6136 2.7126 2.8116 2.9106 2
1.2440 2.1400 2.2400 2.3400 2.4400 2.5400 2.6400 2.7400 2.8400 2.9400
CS5150
Electrical Characteristics: 0C < TA < +70C; 0C < TJ < +85C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID2 = VID1 =
VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1F, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT
s
DAC: continued VID3 VID2 VID1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0
VID0 1 0 1 0 1 0
3.0096 3.1086 3.2076 3.3066 3.4056 3.5046
3.0400 3.1400 3.2400 3.3400 3.4400 3.5400
3.0704 3.1714 3.2724 3.3734 3.4744 3.5754
V V V V V V
s VGATE(H) and VGATE(L) Out SOURCE Sat at 100mA Out SINK Sat at 100mA Out Rise Time Out Fall Time Shoot-Through Current Delay VGATE(H) to VGATE(L) Delay VGATE(L) to VGATE(H) VGATE(H), VGATE(L) Resistance VGATE(H), VGATE(L) Schottky
Measure VCC1 - VGATE(L),;VCC2 - VGATE(H) Measure VGATE(H) - VPGnd; VGATE(L) - VPGnd 1V < VGATE(H) < 9V; 1V < VGATE(L) < 9V VCC1 = VCC2 = 12V 9V > VGATE(H) > 1V; 9V > VGATE(L) > 1V VCC1 = VCC2 = 12V Note 1 VGATE(H) falling to 2V; VCC1 = VCC2 = 8V VGATE(L) rising to 2V VGATE(L) falling to 2V; VCC1 = VCC2 = 8V VGATE(H) rising to 2V Resistor to LGnd 20 LGnd to VGATE(H) @ 10mA LGnd to VGATE(L) @ 10mA
1.2 1.0 30 30
2.0 1.5 50 50 50 50 50 100 800
V V ns ns mA ns ns k mV
25 25 50 600
s Soft Start (SS) Charge Time Pulse Period Duty Cycle COMP Clamp Voltage VFFB SS Fault Disable High Threshold s PWM Comparator Transient Response VFFB Bias Current s Supply Current ICC1 ICC2 Operating ICC1 Operating ICC2 s COFF Normal Charge Time Extension Charge Time Discharge Current
(Charge Time/Pulse Period) x 100 VFB = 0V; VSS = 0 VGATE(H) = Low; VGATE(L) = Low
1.6 25 1.0 0.50 0.9
3.3 100 3.3 0.95 1.0 2.5
5.0 200 6.0 1.10 1.1 3.0
ms ms % V V V
VFFB = 0 to 5V to VGATE(H) = 9V to 1V; VCC1 = VCC2 = 12V VFFB = 0V
100 0.3
125
ns A
No Switching No Switching VFB = COMP = VFFB VFB = COMP = VFFB
8.5 1.6 8 2
13.5 3.0 13 5
mA mA mA mA
VFFB = 1.5V; VSS = 5V VSS = VFFB = 0 COFF to 5V; VFB >1V 3
1.0 5.0 5.0
1.6 8.0
2.2 11.0
s s mA
CS5150
Electrical Characteristics: 0C < TA < +70C; 0C < TJ < +85C; 8V < VCC1 < 14V; 5V < VCC2 < 14V; DAC Code: VID2 = VID1 =
VID0 = 1; VID3 = 0; CVGATE(L) and CVGATE(H) = 1nF; COFF = 330pF; CSS = 0.1F, unless otherwise specified. TEST CONDITIONS MIN TYP MAX PARAMETER UNIT
s Time Out Timer Time Out Time Fault Mode Duty Cycle
VFB = VCOMP; VFFB = 2V; Record VGATE(H) Pulse High Duration VFFB = 0V
10 35
30 50
50 65
s %
Note 1: Guaranteed by design, not 100% tested in production.
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
16L SO Narrow & PDIP 1,2,3,4 VID0 - VID3 Voltage ID DAC input pins. These pins are internally pulled up to 5V providing logic ones if left open. The DAC range is 2.14V to 3.54V with 100mV increments. VID0 - VID3 select the desired DAC output voltage. Leaving all 4 DAC input pins open results in a DAC output voltage of 1.244V, allowing for adjustable output voltage, using a traditional resistor divider. Soft Start Pin. A capacitor from this pin to LGnd in conjunction with internal 60A current source provides soft start function for the controller. This pin disables fault detect function during Soft Start. When a fault is detected, the soft start capacitor is slowly discharged by internal 2A current source setting the time out before trying to restart the IC. Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is shorted. No connection. A capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. Fast feedback connection to the PWM comparator. This pin is connected to the regulator output. The inner feedback loop terminates on time. Boosted power for the high side gate driver. High FET driver pin capable of 1.5A peak switching current. Internal circuit prevents VGATE(H) and VGATE(L) from being in high state simultaneously. High current ground for the IC. The MOSFET drivers are referenced to this pin. Input capacitor ground and the source of lower FET should be tied to this pin. Low FET driver pin capable of 1.5A peak switching current. Input power for the IC and low side gate driver. Signal ground for the IC. All control circuits are referenced to this pin. Error amplifier compensation pin. A capacitor to ground should be provided externally to compensate the amplifier. Error amplifier DC feedback input. This is the master voltage feedback which sets the output voltage. This pin can be connected directly to the output or a remote sense trace.
5
SS
6 7 8 9 10
NC COFF VFFB VCC2 VGATE(H)
11
PGnd
12 13 14 15 16
VGATE(L) VCC1 LGnd COMP VFB
4
CS5150
Block Diagram
VCC2 VCC1
+ 3.90V 3.85V VCC1 Monitor Comparator
5V
60A 0.7V +
SS Low Comparator R S Q Q
VGATE(H)
FAULT FAULT PGnd
SS
2A + SS High Comparator
FAULT Latch
VCC1
VID0 VID1 VID2 VID3
4 BIT DAC + PWM Comparator Slow Feedback + Error Amplifier 2.5V
VGATE(L)
PGnd
VFB COMP VFFB
Maximum On-Time Timeout Normal Off-Time Timeout
R S
Q Q PWM Latch
GATE(H) = ON GATE(H) = OFF COFF One Shot R S Q
Fast Feedback
+
Extended Off-Time Timeout VFFB Low Comparator
Off-Time Timeout
COFF
LGnd
1V
PWM COMP
Time Out Timer (30s)
Edge Triggered
Applications Information Theory of Operation V2TM Control Method The V2TM method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current.
PWM Comparator + C - Ramp Signal COMP Error Signal VGATE(H) VGATE(L)
VFFB
Output Voltage Feedback VFB -
Error Amplifier E
+
Reference Voltage
Figure 1: V2TM Control Diagram
The V2TM control method is illustrated in Figure 1. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2TM control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2TM control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sens5
CS5150
Applications Information: continued ing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2TM method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. Constant Off Time To maximize transient response, the CS5150 uses a constant off time method to control the rate of output pulses. During normal operation, the off time of the high side switch is terminated after a fixed period, set by the COFF capacitor. To maintain regulation, the V2TM control loop varies switch on time. The PWM comparator monitors the output voltage ramp, and terminates the switch on time. Constant off time provides a number of advantages. Switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. Both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. PWM slope compensation to avoid sub-harmonic oscillations at high duty cycles is avoided. Switch on time is limited by an internal 30s timer, minimizing stress to the power components. Programmable Output The CS5150 is designed to provide two methods for programming the output voltage of the power supply. A four bit on board digital to analog converter (DAC) is used to program the output voltage from 2.14V to 3.54V in 100mV steps, depending on the digital input code. If all four bits are left open, the CS5150 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB and VFFB pins, as in traditional controllers. The CS5150 is specifically designed to be upwards compatible with the CS5155, which uses a five bit DAC code. Start Up Until the voltage on the VCC1 supply pin exceeds the 3.9V monitor threshold, the soft start and gate pins are held low. The FAULT latch is reset (no Fault condition). The output of the error amplifier (COMP) is pulled up to 1V by the comparator clamp. When the VCC1 pin exceeds the monitor threshold, the GateH output is activated, and the soft start capacitor begins charging. The GateH output will remain on, enabling the NFET switch, until terminated by either the PWM comparator, or the maximum on time timer. If the maximum on time is exceeded before the regulator output voltage achieves the 1V level, the pulse is terminated. The GateH pin drives low, and the GateL pin drives high for the duration of the extended off time. This time is 6 set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. The GateL pin will then drive low, the GateH pin will drive high, and the cycle repeats. When regulator output voltage achieves the 1V level present at the COMP pin, regulation has been achieved and normal off time will ensue. The PWM comparator terminates the switch on time, with off time set by the COFF capacitor. The V2TM control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. The soft start and COMP capacitors will charge to their final levels, providing a controlled turn on of the regulator output. Regulator turn on time is determined by the COMP capacitor charging to its final value. Its voltage is limited by the soft start COMP clamp and the voltage on the soft start pin (see Figures 2 and 3).
Trace 1 - Regulator Output Voltage (1V/div.) Trace 2 - Inductor Switching Node (2V/div.) Trace 3 - 12V input (VCC1 and VCC2) (5V/div.) Trace 4 - 5V Input (1V/div.)
Figure 2: CS5150 demonstration board startup in response to increasing 12V and 5V input voltages. Extended off time is followed by normal off time operation when output voltage achieves regulation to the error amplifier output.
Trace 1 - Regulator Output Voltage (1V/div.) Trace 3 - COMP Pin (error amplifier output) (1V/div.) Trace 4 - Soft Start Pin (2V/div.)
Figure 3: CS5150 demonstration board startup waveforms.
CS5150
Applications Information: continued If the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see Figure 4).
Trace1 - Regulator Output Voltage (10V/div.) Trace 2 - Inductor Switching Node (5V/div.)
Figure 6: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 13A (heavy load).
Trace 1 - Regulator Output Voltage (5V/div.) Trace 2 - Inductor Switching Node (5V/div.)
Figure 4: CS5150 demonstration board enable startup waveforms.
Normal Operation During normal operation, switch off time is constant and set by the COFF capacitor. Switch on time is adjusted by the V2TM control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current working into the ESR of the output capacitors (see Figures 5 and 6).
Trace 1 - Regulator Output Voltage (10V/div.) Trace 2 - Inductor Switching Node (5V/div.)
Figure 5: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 0.5A (light load).
Transient Response The CS5150 V2TM control loop's 100ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called "adaptive voltage positioning". This technique pre-positions the output capacitor's voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1% allows the error amplifier's reference voltage to be targeted +40mV high without compromising DC accuracy. A "droop resistor", implemented through a PC board trace, connects the error amplifier's feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the error amplifier's, including the +40mV offset. When the full load current is delivered, an 80mV drop is developed across this resistor. This results in output voltage being offset -40mV low. The result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre-positioned +40mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre-positioned -40mV (see Figures 7, 8, and 9). For best transient response, a combination of a number of high frequency and bulk output capacitors are usually used.
7
CS5150
Applications Information: continued If the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor.
Trace1 - Regulator Output Voltage (1V/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 3 - Output Current (13 to 0.5 Amps) (20V/div.)
Trace 1 - Regulator Output Voltage (1V/div.) Trace 3 - Regulator Output Current (20V/div.)
Figure 9: CS5150 demonstration board response to 13A load turn off (output set for 2.8V). V2TM control topology immediately connects inductor to ground, providing 0% duty cycle. Regulation is achieved in less than 10s.
Figure 7: CS5150 demonstration board response to a 0.5 to 13A load pulse (output set for 2.8V).
Protection and Monitoring Features VCC1 Monitor To maintain predictable startup and shutdown characteristics an internal VCC1 monitor circuit is used to prevent the part from operating below 3.75V minimum startup. The VCC1 monitor comparator provides hysteresis and guarantees a 3.70V minimum shutdown threshold. Short Circuit Protection A lossless hiccup mode short circuit protection feature is provided, requiring only the soft start capacitor to implement. If a short circuit condition occurs (VFFB < 1V), the VFFB low comparator sets the FAULT latch. This causes the top MOSFET to shut off, disconnecting the regulator from its input voltage. The soft start capacitor is then slowly discharged by a 2A current source until it reaches its lower 0.7V threshold. The regulator will then attempt to restart normally, operating in its extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60A charge current. If the short circuit condition persists, the regulator output will not achieve the 1V low VFFB comparator threshold before the soft start capacitor is charged to its upper 2.5V threshold. If this happens the cycle will repeat itself until the short is removed. The soft start charge/discharge current ratio sets the duty cycle for the pulses (2A/60A = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%).
Trace 1 - Regulator Output Voltage (1V/div.) Trace 2 - Inductor Switching Node (5V/div.) Trace 3 - Output Current (0.5 to 13 Amps) (20V/div.)
Figure 8: CS5150 demonstration board response to 13A load turn on (output set for 2.8V). Upon completing a normal off time, the V2TM control loop immediately connects the inductor to the input voltage, providing 100% duty cycle. Regulation is achieved in less than 20s.
8
CS5150
Applications Information: continued This protection feature results in less stress to the regulator components, input power supply, and PC board traces than occurs with constant current limit protection (see Figures 10 and 11). If the short circuit condition is removed, output voltage will rise above the 1V level, preventing the FAULT latch from being set, allowing normal operation to resume. ed, resulting in a "crowbar" action to clamp the output voltage and prevent damage to the load (see Figures 12 and 13). The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. The bottom FET and board trace must be properly designed to implement the OVP function.
Trace 4 - 5V Supply Voltage (2V/div.) Trace 3 - Soft Start Timing Capacitor (1V/div.) Trace 2 - Inductor Switching Node (2V/div.)
Trace 4 = 5V from PC Power Supply (5V/div.) Trace1 = Regulator Output Voltage (1V/div.) Trace 2 = Inductor Switching Node (5V/div.)
Figure 10: CS5150 demonstration board hiccup mode short circuit protection. Gate pulses are delivered while the soft start capacitor charges, and cease during discharge.
Figure 12: OVP response to an input-to-output short circuit by immediately providing 0% duty cycle, crow-barring the input voltage to ground.
Trace 4 = 5V from PC Power Supply (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.)
Trace 4 = 5V from PC Power Supply (2V/div.) Trace 2 = Inductor Switching Node (2V/div.)
Figure 13: OVP response to an input-to-output short circuit by pulling the input voltage to ground.
Figure 11: Startup with regulator output shorted.
Overvoltage Protection Overvoltage protection (OVP) is provided as result of the normal operation of the V2TM control topology and requires no additional external components. The control loop responds to an overvoltage condition within 100ns, causing the top MOSFET to shut off, disconnecting the regulator from its input voltage. The bottom MOSFET is then activat-
External Output Enable Circuit On/off control of the regulator can be implemented through the addition of two additional discrete components (see Figure 14). This circuit operates by pulling the soft start pin high, and the VFFB pin low, emulating a short circuit condition.
9
CS5150
Applications Information: continued
5V
MMUN2111T1 (SOT-23)
5
SS
CS5150
8V FFB
IN4148
Shutdown Input
Figure 14: Implementing shutdown with the CS5150.
External Power Good Circuit An optional Power Good signal can be generated through the use of four additional external components (see Figure 15). The threshold voltage of the Power Good signal can be adjusted per the following equation: VPower Good = (R1 + R2) x 0.65V R2
Trace 3 = 12V Input (VCC1) and VCC2) (10V/div.) Trace 4 = 5V Input (2V/div.) Trace 1 = Regulator Output Voltage (1V/div.) Trace 2 = Power Good Signal (2V/div.)
Figure 16: CS5150 demonstration board during power up. Power Good signal is activated when output voltage reaches 1.70V.
This circuit provides an open collector output that drives the Power Good output to ground for regulator voltages less than VPower Good.
5V R3 10k R1 10k VOUT Power Good
Selecting External Components The CS5150 can be used with a wide range of external power components to optimize the cost and performance of a particular design. The following information can be used as general guidelines to assist in their selection. NFET Power Transistors Both logic level and standard MOSFETs can be used. The reference designs derive gate drive from the 12V supply which is generally available in most computer systems and utilize logic level MOSFETs. A charge pump may be easily implemented to support 5V only systems. Multiple MOSFETs may be paralleled to reduce losses and improve efficiency and thermal management. Voltage applied to the MOSFET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5V of ground when in the low state and to within 2V of their respective bias supplies when in the high state. In practice, the MOSFET gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller IC. For the typical application where VCC1 = VCC2 = 12V and 5V is used as the source for the regulator output current, the following gate drive is provided; VGATE(H) = 12V - 5V = 7V, VGATE(L) = 12V (see Figure 17).
PN3904 R2 6.2k
PN3904
CS5150
Figure 15: Implementing Power Good with the CS5150.
10
CS5150
Applications Information: continued COFF timing capacitor: COFF = where: Period = 1 switching frequency Period x (1 - duty cycle) , 4848.5
Trace 3 = VGATE(H) (10V/div.) Math 1= VGATE(H) - 5VIN Trace 4 = VGATE(L) (10V/div.) Trace 2 = Inductor Switching Node (5V/div.)
Figure 17: CS5150 gate drive waveforms depicting rail to rail swing.
The most important aspect of MOSFET performance is RDSON, which effects regulator efficiency and MOSFET thermal management requirements. The power dissipated by the MOSFETs may be estimated as follows; Switching MOSFET: Power = ILOAD2 x RDSON x duty cycle Synchronous MOSFET: Power = ILOAD2 x RDSON x (1 - duty cycle) Duty Cycle =
VOUT + (ILOAD x RDSON OF SYNCH FET) VIN + (ILOAD x RDSON OF SYNCH FET) - (ILOAD x RDSON OF SWITCH FET)
Schottky Diode for Synchronous MOSFET A Schottky diode may be placed in parallel with the synchronous MOSFET to conduct the inductor current upon turn off of the switching MOSFET to improve efficiency. The CS5150 reference circuit does not use this device due to its excellent design. Instead, the body diode of the synchronous MOSFET is utilized to reduce cost and conducts the inductor current. For a design operating at 200kHz or so, the low non-overlap time combined with Schottky forward recovery time may make the benefits of this device not worth the additional expense (see Figure 6, channel 2). The power dissipation in the synchronous MOSFET due to body diode conduction can be estimated by the following equation: Power = Vbd x ILOAD x conduction time x switching frequency Where Vbd = the forward drop of the MOSFET body diode. For the CS5150 demonstration board as shown in Figure 6; Power = 1.6V x 13A x 100ns x 233kHz = 0.48W This is only 1.3% of the 36.4W being delivered to the load. "Droop" Resistor for Adaptive Voltage Positioning Adaptive voltage positioning is used to reduce output voltage excursions during abrupt changes in load current. Regulator output voltage is offset +40mV when the regulator is unloaded, and -40mV at full load. This results in increased margin before encountering minimum and maximum transient voltage limits, allowing use of less capacitance on the regulator output (see Figure 7). To implement adaptive voltage positioning, a "droop" resistor must be connected between the output inductor and output capacitors and load. This is normally implemented by a PC board trace of the following value: RDROOP = 80mV IMAX
Off Time Capacitor (COFF) The COFF timing capacitor sets the regulator off time: TOFF = COFF x 4848.5 When the VFFB pin is less than 1V, the current charging the COFF capacitor is reduced. The extended off time can be calculated as follows: TOFF = COFF x 24,242.5. Off time will be determined by either the TOFF time, or the time out timer, whichever is longer. The preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the
Adaptive voltage positioning can be disabled for improved DC regulation by connecting the VFB pin directly to the load using a separate, non-load current carrying circuit trace.
11
CS5150
Applications Information: continued Input and Output Capacitors These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. Key specifications for input capacitors are their ripple rating, while ESR is important for output capacitors. For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. Output Inductor The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Thermal Management Thermal Considerations for Power MOSFETs and Diodes In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: Thermal Impedance = TJUNCTION(MAX) - TAMBIENT Power Layout Guidelines 1. Place 12V filter capacitor next to the IC and connect capacitor ground to pin 11 (PGnd). 2. Connect pin 11 (PGnd) with a separate trace to the ground terminals of the 5V input capacitors. 3. Place fast feedback filter capacitor next to pin 8 (VFFB) and connect its ground terminal with a separate, wide trace directly to pin 14 (LGnd). 4. Connect the ground terminals of the Compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the PWM comparator. 5. Place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (LGnd). 6. To implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (VFB) and 8 (VFFB) to the regulator output right at the inductor terminal. Connect inductor to the output capacitors via a trace with the following resistance: RTRACE = 80mV IMAX
A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. EMI Management As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions.
This causes the output voltage to be +40mV with no load, and -40mV with a full load, improving regulator transient response. This trace must be wide enough to carry the full output current. (Typical trace is 1.0 inch long, 0.17 inch wide). Care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. If DC regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to VFB pin directly to the load with a separate trace (remote sense). 8. Place 5V input capacitors close to the switching MOSFET and synchronous MOSFET. Route gate drive signals VGATE(H) (pin 10) and VGATE(L) (pin 12 when used) with traces that are a minimum of 0.025 inches wide.
VCC 0.1F
15
To the negative terminal of the input capacitors
11
1.0F VCOMP 100pF VFFB
8 5
SOFTSTART
OFF TIME
To the negative terminal of the output capacitors
2H
2H +
Figure 20: Layout Guidelines
33 1000pF
1200F x 3/16V
Figure 18: Filter components
Figure 19: Input Filter
12
CS5150
Additional Application Circuits
5V 12V 0.1F MBRS 120 MBRS120 1F VCC1 VID0 VID1 VID2 VID3 COFF 330pF VCC2 VGATE(H) MBRS120 1F Si4410DY 3H 3.3V/10A + 100F/10V x 3 Tantalum Si9410 VCC1 VID0 VID1 VID2 Si9410DY 330pF PGnd SS 0.1F 0.33F COMP LGnd VFB VFFB 3.3k + 0.1F 0.33F SS COMP LGnd 100pF 100F/10V x 3 Tantalum PGnd VFFB 3.3k VID3 COFF VGATE(L) Si9410 VCC2 VGATE(H) 5H 2.5V/7A 1F + 33F/25V x 3 Tantalum 3.3V
CS5150
VGATE(L)
CS5150
VFB
+
100F/10V x 2 Tantalum
100pF
Figure 21: 5V to 3.3V/10A converter.
Figure 23: 3.3V to 2.5V/7A converter with 12V bias.
5V
0.1F MBRS 120 MBRS120 1F VCC1 VID0 VID1 VID2 VID3
MBRS120 1F Si4410 VCC2 VGATE(H) 3H + 100F/10V x 3 Tantalum
Remote Sense 3.3V/10A
CS5150
VFB
10 Si9410
+
COFF 330pF
100F/10V x 3 Tantalum
VGATE(L)
SS 0.1F 0.33F COMP LGnd
PGnd VFFB 3.3k Connect to other circuits for current sharing
100pF
Figure 22: 5V to 3.3V/10A converter with current sharing.
13
CS5150
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES) PACKAGE THERMAL DATA
D Lead Count 16L SO Narrow 16L PDIP Metric Max Min 10.00 9.80 19.69 18.67 English Max Min .394 .386 .775 .735
Thermal Data RJC RJA typ typ
16L SO Narrow 28 115
16L PDIP 42 80
C/W C/W
Surface Mount Narrow Body (D); 150 mil wide
4.00 (.157) 3.80 (.150)
6.20 (.244) 5.80 (.228)
0.51 (.020) 0.33 (.013)
1.27 (.050) BSC
1.75 (.069) MAX 1.57 (.062) 1.37 (.054) 1.27 (.050) 0.40 (.016) 0.25 (.010) 0.19 (.008) D REF: JEDEC MS-012
0.25 (0.10) 0.10 (.004)
Plastic DIP (N); 300 mil wide
7.11 (.280) 6.10 (.240)
8.26 (.325) 7.62 (.300) 3.68 (.145) 2.92 (.115)
1.77 (.070) 1.14 (.045)
2.54 (.100) BSC
.356 (.014) .203 (.008)
0.39 (.015) MIN. .558 (.022) .356 (.014) Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same.
REF: JEDEC MS-001
D
Ordering Information
Part Number CS5150GD16 CS5150GDR16 CS5150GN16
Rev. 1/4/99
Description 16L SO Narrow 16L SO Narrow (tape & reel) 16L PDIP 14
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
(c) 1999 Cherry Semiconductor Corporation

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